The current method of transfer of data and timing information between Physical Medium Dependent (PMD) and Transmission Convergence (TC) sublayers requires serial transmission of frame payload qualified with clock and frame pulse indications. A separate set of these signals is required in both directions for each port or physical link.
For example, digital signals are often multiplexed to produce higher bit rates for higher capacity transmission systems, as a means of utilizing the same transmission medium economically for many different users. This multiplexing is one of functions that perform such data transfer. Different digital signal hierarchies were developed in North America, Europe and other parts of the world. In North America, DS1,DS2 and DS3 whose bandwidths are respectively 1.544 Mbit/sec., 6.312 Mbit/sec. and 44.736 Mbit/sec. are used. Transmission services which provide these digital signals are called T1, T2 and T3. DS0 is a basic TDM signal (voice channel signal) of 64 Kbit/sec. Thus, 24 DS0 streams are multiplexed to one DS1,four of which are combined into one DS2. Seven DS2 streams are multiplexed to one DS3 stream. At each multiplexing operation, certain overhead bit or bits are added for framing, synchronization and other housekeeping functions. In some multiplexing operations, certain payload databits are borrowed for housekeeping functions as well.
According to "Four channel DS1 Framer" Eugene L. Parrella et al, IEEE International ASIC Conference and Exhibit:
"Wideband telecommunications services such as T3, SONET, and inverse multiplexed T1 services are driving more highly integrated multichannel T1 cards. With the availability of single chip M13 (T1/T3) multiplexers and multichannel SONET mappers, T1 framers and T1 line interface units may become the bottlenecks to further reductions in card size, power and cost. A multichannel T1 framer offers substantial board area reduction, and is highly desirable if competitive in power consumption and cost to multiple single channel framers. PA1 As an example, a DS0-T3 switching application can be considered. A single chip M13 multiplexer is employed, multiplexing 28 DS1s into a DS3. To convert DS0's into 28 framed DS1's, 28 DS1 framers are required. A multichannel framer can be used effectively to lower parts count for the system."
Therefore, the above application of DS1-DS3 interface requires 112 connections between a group of 7 quad DS1 framers and a M13 multiplexer.
The present invention permits the transfer of data and timing information between the PMD and TC sublayers, a predetermined sized block of data at a time. Each data block is uniquely identified with an identification number which specifies the port or physical link with which it is associated and the position of the data block within the frame (if the transfer is one of framed data). Timing information is passed between the two sublayers in digital representation form. It represents an offset with respect to a reference clock which can be board, system, or network wide.
This invention greatly reduces the number of signals required between the two sublayer devices. This makes it physically possible to increase the number of ports serviced by PMD and TC sublayer devices by greatly reducing their pin count requirements.
In one embodiment, the present invention permits interfacing between digital signals of two different hierarchical levels very efficiently. In particular, as an example, in a DS1-DS3 interface only 24 lines (instead of 112 connections mentioned above) are required, running at a reasonable speed of 50 MHz.
Furthermore, for channelized applications, the necessity to demultiplex onto separate asynchronous bit streams only to multiplex back to one synchronous stream has been eliminated.